Description
TL;DR: A hardware-oriented synchronization scheme combining low-frequency self-stabilization with high-frequency accurate clock generation.
About This Document
Danny Dolev, Matthias Függer, Christoph Lenzen, Markus Posch, Ulrich Schmid, and Andreas Steininger design FATAL+ for critical systems-on-chip. The paper provides algorithms, proofs, implementation details, and performance analysis while confronting hardware effects such as metastability and asynchronous communication among clock domains.
Why Bitcoin People May Care
This is not Bitcoin or transaction consensus. It uses Byzantine-fault-tolerance methods to keep hardware clocks coordinated after transient and malicious faults. The paper is useful adjacent systems research because reliable ordering depends on time and communication assumptions, but its nodes live on a chip rather than an open monetary network. Results apply to its hardware model.
What You Receive
Purchase reveals the verified preserved PDF location for this document.
Document Details
- Title: FATAL+: Byzantine-Fault-Tolerant Clocking for Systems on Chip
- Author / organization: Danny Dolev, Matthias Függer, Christoph Lenzen, Markus Posch, Ulrich Schmid, and Andreas Steininger
- Year: 2012
- Language: English
- Document type: Fault-tolerant hardware research paper
- Pages: 40
CacheRat provides researched source-location and document-identification information. CacheRat does not claim ownership of the underlying third-party documentation.


